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VLSI JOBS

Role : VLSI Design Engineers
Location : bangalore
Experince : 3-8 years
Salary : 5-25 lakhs
Details : General logic design concepts and experience in FPGA logic design • Experience in STA/Synthesis • Synthesis experience for Timing closure • Experience in using TCL/Perl. Basic Job Deliverable : • Should be able to analyze the timing failures, CDC and lint issues. • Should be able to understand the TCL files and strong debugging skills is desired
Role : Application Engineer
Location : Banaglore and Noida
Experince : 0-2 Years
Salary : 0-6 lakh
Details : Application Engineer job opening at Synopsys, Noida Experience: 1 year or M.tech with Intern experience in timing, synthesis, formality, LEC, formal verification can also apply.
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