VLSIcareer is a premier platform for higher learning in VLSI / ASIC design and verification. The training programs cover the advanced latest tools and technologies in VLSI training.

VLSIcareer revered platform in the field of VLSI/ASIC training aims to provide world-class education with an optimum level of research, creativity, and service for this sector. VLSI/ASIC Design and verification is an extremely challenging role, which will be developing the next generation Intellectual property.

ASIC Design & Verification Course Overview:
1. ASIC Design & Verification Course

The term ASIC stands for Application Specific Integrated Circuit. It is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.

In ASIC Design and Verification process, Verification consumes 50% to 70% of the effort of design cycle and is on the critical path in the design flow of multimillion gate ASICs. Hence verification has become the main bottleneck in the design process.

The functional verification bottleneck is an effect of raising the design abstraction level. Majority of ASICs require at least one re-spin, and with 71% of re-spins are due to functional bugs.

An ASIC Verification methodology provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments. FPGA Emulation is another means of verifying complex ASICs, and it helps to capture real time bugs.

Vlsicareeris now offering career courses geared towards meeting this rising global demand.

Digital VLSI Courses

1. ASIC Design Verification

Course Outline:

    Module 1
  • Basic design support systems –Unix/Linux, Text editors
  • Perl Scripting Language
    Module 2
  • Digital Fundamentals
  • Digital Design
    Module 3
  • HDL(Verilog)
  • HDL for design, Verification
  • Designing using HDL
    Module 4
  • Designing for synthesis
  • Basic Checks on the HDL code
    Module 5
  • Design from Spec
  • Design support tools – Code version management
  • Basic Verification flow and associated planning
  • Mini Project – Design verification
  • Design support tools – Bug tracking
  • Debug techniques
    Module 6
  • System Verilog – Basic
  • System Verilog for Verification
  • System Verilog Verification project
    Module 7
  • UVM Basics
  • Automation in verification
  • UVM Advanced
  • UVM – Mini Project
    Module 8
  • Course ending project
  • Gate Level simulations and Challenges
  • Advanced topics
  • Formal Verification
  • Potable Simulations
  • Importance of Emulation
  • Low power verification techniques
  • Guest Lectures
    Module 9
  • Soft skills
    Tools to be used:
  • Simulation based verification tools from industry leading vendor
  • Static design checker/verification tools
2. Physical Design

Course Outline:

    Module 1: CMOS fundamentals & Introduction to Physical Design
  • MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow
    Module 2: Inputs & Sanity Check
  • List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, contents of each input, qualifying the received inputs and sanity checks
    Module 3: Floorplan
  • Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines
    Module 4: Power Routing
  • Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail
    Module 5: Placement
  • Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis,Scan chain re-order, Regioning/Grouping/Bounds.
    Module 6: Timing Analysis & Optimization
  • Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same
    Module 7: Clock Tree Synthesis (CTS)
  • Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.
    Module 8: Routing
  • Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.
    Module 9: ECO Flow
  • What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing
    Module 10: Sign-off Checks
  • Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking
    Module 11: Project
  • 2 projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks
    Tools to be used:
  • Leading EDA Physical Design Tools will be used
  • Additional Lab Hours through VPN
3. Design for test(DFT)
SCAN & JTAG Insertion

Course Outline:

    Week 1
  • Full ASIC flow – DFT
  • DFT Basics
  • Understanding of SCAN in depth
  • Scan architecture overview
  • Types of Scan
  • Scan golden rules
    Week 2
  • Understanding and analysis of DFT DRC
  • Multiple clock handling
  • DRC Fixing with examples
  • Full scan insertion and stitching without compression
  • Generate test protocol and understanding
    Week 3
  • Designing using HDL
  • Basics/Need of Compression
  • Compression techniques
  • Scan insertion with compression
  • On-chip clocking for at-speed testing
    Week 4
  • Hierarchical Scan Design
  • Top-Down Scan Insertion
  • Boundary scan basics
  • Boundary scan cell operation in detail
  • JTAG basics, operation and state machine
    Tools to be used:
  • Industry Standard DFT Tool set will be used
  • Additional Lab Hours through VPN
ATPG & Simulations

Course Outline:

    Week 1
  • ASIC Flow
  • DFT Overview
  • DFT Flow
  • Understanding of Defects and Faults
  • Functional test Vs Structural Test
  • ATPG
  • Understanding of Silicon testing from Tester to gate level
  • Fault Detection
  • Faults and fault collapsing
  • ATPG algorithm
    Week 2
  • Fault models
  • Types of fault models
  • Different types of ATPG
  • Stuckat fault model with an example
  • Understanding of ATPG constraints
  • Understanding of SPF
  • ATPG DRC analysis [2-3 Live examples]
  • ATPG for Stuckat fault model
  • Test Coverage Vs Fault Coverage
    Week 3
  • Usage of ATPG Graphical schematic viewer
  • Analyzing feedback paths
  • ATPG pattern simulation flow
  • Stuckat pattern Simulation and failure debugging
  • Analyzing ATPG faults
  • Coverage improvement techniques
  • ATPG pattern optimization
    Week 4
  • At speed fault models
  • Understanding Transition fault ATPG
  • ATPG setup for transition fault model
  • ATPG for Transition fault model
  • Timing exceptions in atspeed testing
  • Path delay fault modelling
  • On-Chip clock controller
    Week 5
  • Transition Pattern simulation
  • Transition pattern Simulation failure debugging
  • Introduction to Diagnosis
  • Diagnosis Flow
  • Analysing failure logs
    Tools to be used:
  • Industry Standard DFT Tool set will be used
  • Additional Lab Hours through VPN
4. Synthesis sign-off STA and LEC
    Synthesis (3 weeks) :
  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining Design for timing area & power
  • Understanding & Exploring .lib
  • Synthesize Design
  • Timing Checks
  • Report, Analyze and debug results
  • Optimization Techniques
  • Low Power Synthesis using UPF
  • Understanding the UPF and low power concepts
  • Understanding of Low power cells and their requirement
  • Low power synthesis using UPF file
  • Scan Insertion
    Formal Verification (Equivalence Check) (0.5 Weeks)
  • Loading reference & implemented design
  • Understanding & Matching compare points
  • Verifying design & interpreting results
  • Debugging Verification
    Static Timing Analysis (3.5 weeks) :
  • STA overview & concepts
  • Clocking – Handling clock muxes, clock dividers
  • Generated clocks, Clocking Exceptions
  • Timing Exceptions
  • Post Layout STA using SPEF
  • Multi Mode, Multi Corner STA
  • Derates, OCV, Variations – Source and cause
  • Crosstalk & Noise Analysis
  • Timing ECOs generation, What-If Analysis
  • Timing Challenges
    Tools to be used:
  • Industry Standard Tools
  • Additional Lab Hours through VPN
5. TCL Scripting
Course Content outline

This course is designed and delivered, as application oriented with hands on labs using prime time, by writing TCL scripts for day to day problems.

After covering the basics of TCL, trainer teaches, how to write small scripts in prime time and slowly increases the complexity of scripts, by using prime time commands. Trainer takes some problem statements from your day to day VLSI work and teaches how to write scripts quickly for such requirements.

  • Basics of TCL
  • How to write small scripts in TCL
  • How to write TCL scripts by using prime time commands
  • How to understand complex TCL scripts and debug / modify them as needed
  • Best practices in writing TCL scripts
  • How to develop own commands, for your custom requirements
    Tools to be used:
  • Industry Standard Tools will be used
6. Verification using system Verilog
Course Content outline

Each module has associated hands-on labs

PART-I – Basic Course
    Module 1: Introduction to System Verilog
  • Overview of HDL and HVL, Need for SystemVerilog, SV capabilities and highlights, SV as one solution HDVL.
    Module 2a: System Verilog Basics
  • Lexical Conventions, Data types, Aggregate Data types, Casting, SV operators and their precedence. Processes, Understanding the Procedural statements and control flow, process execution threads and fine grain process controls. Interfaces and Modports, Virtual interfaces, Clocking blocks
    Module 2b: Design and verification building blocks
  • module, program, interface, subroutines, packages, configurations, compilation and elaboration, declaration name spaces, Simulation time, time units and time precision
    Module 3: SV Classes and Randomization and constraints
  • Classes, objects, handles and built-in methods for efficient TB development. Efficient memory management in SV. Different randomization techniques and constructs. Inline randomization, seeding, random methods and random stability
    Module 4: Riding SV on Chariot of OOPS
  • Tasks and functions and their enhancements in system Verilog. Introduction to OOP concepts of data abstraction, data encapsulation, data hiding, inheritance and polymorphism.
    Module 5: Coverage based Verification
  • Introduction to code and functional coverage. Functional coverage in SV. Cover groups, cover points, cover bins and cross coverage constructs. Different ways of sampling the coverage and measuring the verification closure.
PART-II – Advanced Course
    Module 6: Specialized communication packing and bug isolation in SV
  • Interprocess Synchronization and communication – Semaphore, Mailboxes and Named Events, Scheduling semantics Event-based simulation scheduling semantics— SystemVerilog’s stratified event scheduling algorithm— Determinism and nondeterminism of event ordering— Possible sources of race conditions— PLI callback control points.
    Module 7: Faster verification using System Verilog Assertions
  • Introduction to Assertions. Advantages of assertions. Immediate and concurrent assertions. Writing assertion Sequences, Different ways of writing assertions and its constructs and calling methods.
    Module 8: Application Programming Interfaces
  • Introduction to DPIs, DPI layers, importing and exporting mechanism from System Verilog to other language. Usage and advantages of using DPIs and its Limitations.
Tools to be used:
  • Industry Standard Verification Tool Suite
  • Additional Lab Hours through VPN
7. Verification using UVM
Course Content outline
    Module 1: Verification Methodology, UVM Basics
  • Need for a Verification methodology, UVM as a template, introduction and evolution of UVM. Basic concepts of UVM.
    Module 2: UVM Components- Agents, Sequencer, Sequence. Macros, TLM
  • Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building test bench for a real time design with these UVM components
    Module 3: UVM Phasing, UVM Factory and Advanced sequence control
  • Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases.Introduction to Factory, Importance of dynamic binding and factory usage. Registering , creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences
    Module 4: Register Modeling using UVM Register Layer
  • UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.
    Module 5: Reporting, UVCs
  • Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real time example of UVC
    Module 6: Complete UVC building
  • For a given Design, building an UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.
Project Details:

Last 2 days are dedicated exclusively for the project.

  • To develop UVC and TB for a proprietary/customized/non-standard bus protocol
  • Trainees have to develop the UVC using standard UVM components and develop TEST and testcases to test the UVC and its features
  • Integrate DUT (supplied by trainer) with UVC/TB and do full verification as per the vplan (supplied by trainer) and collect code coverage
Tools to be used:
  • Industry standard simulation suite
  • 24×7 lab access through VPN
8. Low power implementation (PD)using UPF
Course Content outline
    Module 1: Low power basics
  • Significance of Low power designs – Use cases; Types of power dissipation; LP Techniques- Power gating, Clock gating, DVFS, Multi-VDD, Multi VT; Power management cells & usage – ISO, LVL, P-Switch, RET, AON.
    Module 2: UPF
  • Why UPF, Power domains, Power state table, Power gating strategies, LVL-ISO strategies, SRSN, Activity – Developing UPF on sample design
    Module 3: Low power implementation techniques
  • P-Switch Daisy chain, Voltage area, ISO-LVL placement, MV-CTS, AON buffering & feedthrough, ECO implementation, Leakage recovery, Dynamic power optimization
    Module 4: Low power checks
  • Introduction to Inrush current analyses and low power signoff checks – Demo of rules in ICC (Power intent checks, Implementation checks)
Tools to be used:
  • Industry Standard Tools will be used


1. CMOS Analog circuit design

Course Outline:

    Week 1: Device Basics
  • Refreshing MOS basics.
  • Circuit Design Tool Flow Introduction.
  • MOS Device Characterisation using simulation.
    Week 2: Analog Circuit Basics
  • Design of Single Ended MOS Amplifiers.
  • Common Source (CS) Amplifier Design for various design parameters
  • Identify practical difficulties and constraints (Size, power, etc)
  • Introduction to other Single Ended Amplifiers.
    Week 3: Analog Circuit Basics
  • Design of Differential Amplifiers
  • Extended CS Amplifier concept to differential amp
  • Understanding common mode and differential signalling
  • Design and identify usage and importance of differential amplifier
    Week 4: Analog Building Blocks
  • Design and Verification of OTA/Operational Amplifier
  • Build the design based learning of CS amplifier and Diff Amp
  • Understand application of OTA/OpAmp in various system designs
    Week 5: Analog Building Blocks
  • Design and Verification of Band gap reference
    Week 6: Analog Building Blocks
  • Design and Verification of Analog Comparator
  • Apply the learning of OTA, diff amp etc. and build an analog comparator
  • Understand various architectures and limitations of comparator
  • Understand applications of comparator in various Analog Designs (like ADC)
    Week 7: Analog Building Blocks
  • Design and Verification of Oscillator Circuit
  • Learn designing a ring based voltage controlled oscillator
  • Understand limitations and advantage of each architecture
  • Understand usage of VCO in PLL
    Week 8: (Project Work)
  • Introduction to Analog IP/Module using Analog Building blocks
  • Project work on selected design/topic
    Tools to be used:
  • Full custom design environment from leading EDA vendor, with hspice as simulator
  • Additional Lab Hours through VPN
2. High speed IO circuit design

Course Outline:

Module 1:
    Week 1
  • Lecture : Introduction to IO Cells, Specifications, Contents of IO Library (various views and use), Basics of MOS devices (Brush up of basics), Spice Simulation Basics
  • Lab: Schematic draw and simulation of inverter
    Week 2
  • Lecture : Design of O/P driver, pre-driver and level shifter circuit, Design of Receiver Circuit
  • Lab: Design, simulation and verification of O/P driver, pre-driver and level shifter circuit
    Week 3
  • Lecture : for ESD, Packaging effects, High Speed IO
  • Lab: Design, simulation and verification of receiver circuit, Verification of remaining part of output structure
Module 2: Basics of Analog Design
    Week 4
  • Lecture : Device Characterisation, Current Mirror
  • Lab: Device characterisation by simulation and current mirror
    Week 5
  • Lecture : Amplifier basics and stability analysis theory
  • Lab: Circuit design and verification of amplifier for all the parameters
Module 3: High Speed IO Circuits–CML Driver and Receiver
    Week 6
  • Lecture : Specification of CML Driver Circuits and challenges
  • Lab: Design and verify CML Driver (Final stage)
    Week 7
  • Lecture : Complete the Design and verification of Multi stage CML Driver
  • Lab: Complete the Design and verification of Multi stage CML Driver
    Week 8
  • Lecture : Introduction to jitter and jitter analysis in SERDES, Q&As and tips on building career in Analog Circuit Design
  • Lab: Design and Verification of CML Receiver
    Tools to be used:
  • Industry Standard Tools
  • Additional Lab Hours through VPN
3. Analog layout design

Course Outline:

    Week 1 : Fabrication Process
  • Basic steps of IC fabrication
  • CMOS IC fabrication
  • Deep Submicron Technology
    Week 2 : Layout Editor Tool
  • Creating and managing libraries and cell.
  • Commands for Layout editing.
  • Commands for schematic editing.
  • Verification : DRC and LVS
    Week 3 : Layout or Physical Implementation
  • Understanding the schematic symbols and parameters
  • Resistor, Capacitor layout techniques
  • Cmos and BiCMOS layout techniques
    Week 4 : Standard Cell Layout
  • Layout of Inverter, AND, OR, NAND, NOR, AOI, OAI, LATCH, FLOP
    Week 5 : Matching
  • Matching techniques
  • common centriod, interdigitized and proximity matching.
  • Matching of Resistors, Capacitors
  • Matching of mos transistors
    Week 6: Complex Layout enemies
  • Electro-migration
  • Power/Signal IR Drop
  • cross-talk and coupling
  • Electrostatic Discharge
    Week 7 : Deep Submicron Layout Issues
  • Shallow Trench Isolation (LOD)
  • Well Proximity Effect.
    Week 8 : Analog and Mix signal Layout
  • Single stage differential opamp layout
  • Input pair, current mirrors and output stage.
  • Two stage differential opamp layout
  • Input pair, differential routing, Power routing, offset minimizing
    Week 9 : Building blocks of SRAM
  • Memory Bit cell
  • Row decoder
  • Word line driver
  • Sense amplifier
  • Control block
  • Misc digital logic.
  • Pitch Calculation for blocks.
  • Power Planning
  • Assignments based on above theory.
    Week 10 : Project
  • Analog Projects like LDO, Op-amp & other similar size projects will be executed in latest technology nodes.
  • Std layouts will be done as part of labs & assignments. No separate project will be executed
    Tools to be used:
  • Industry standard Layout tools will be used
  • Additional Lab Hours through VPN

ASIC Design & Verification

1. ASIC Design & Verification [ASIC-DV] 2. ASIC Design & Verification [ASIC-G2SIDV]




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